• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    system and method for energy-selective memory channel interleaving or performance optimization. Systems and methods are described for providing energy-selective memory channel interleaving or performance optimization. one method involves configuring a memory address map for two or more memory devices accessed through two or more respective memory channels with an interleaved region and a linear region. the interleaved region comprises an interleaved address space for relatively higher performance use cases. the linear region comprises a linear address space for relatively lower power usage cases. memory requests are received from one or more clients. memory requests comprise a preference for energy savings or performance. incoming memory requests are assigned to the linear region or interleaved region according to power saving or performance preference.
    公开号:BR112016002454B1
    申请号:R112016002454-0
    申请日:2014-08-07
    公开日:2022-01-04
    发明作者:Dexter Chun；Yanru Li；Alex Tu；Haw-Jing Lo
    申请人:Qualcomm Incorporated；
    IPC主号:
    专利说明:

    Description of Related Technique
    [0001] Many computing devices, including portable computing devices such as mobile phones, include a System on Chip ("SoC"). SoCs demand ever-increasing power performance and ever-increasing capacity from memory devices, such as dual data rate (DDR) memory devices. These demands result in both higher clock speeds and wider buses, which are then typically split into multiple, narrower memory channels in order to remain efficient. Multiple memory channels can be address interleaved together to evenly distribute memory traffic across memory devices and optimize performance. Memory data is evenly distributed by assigning addresses to switch memory channels. This technique is commonly referred to as symmetric channel interleaving.
    [0002] Existing symmetric memory channel interleaving techniques require all channels to be enabled. For high performance use cases, this is intentional and necessary to achieve the desired level of performance. For low-performance use cases, however, this results in wasted energy and inefficiency. Accordingly, there remains a need in the art for improved systems and methods for providing memory channel interleaving. Description Summary
    [0003] Systems and methods are described to provide energy-selective memory channel interleaving or performance optimization. One modality is a method of energy-selective or performance-optimized memory channel interleaving. Such a method comprises: configuring a memory address map for two or more memory devices accessed through two or more respective memory channels with an interleaved region and a linear region, the interleaved region comprising an interleaved address space for relatively higher performance use cases and the linear region comprising a linear address space for relatively lower power use cases; receiving memory requests from one or more clients, the memory requests comprising a preference for energy savings or performance; and assigning memory requests to the linear region or the interleaved region according to the preference for power savings or performance.
    [0004] Another embodiment is a system for providing energy selective memory channel interleaving or performance optimization. Such a system comprises a System on Chip (SOC), a memory address map, and a memory channel interleaver. The SoC comprises one or more processing units for generating memory requests to access two or more external memory devices connected to the SoC and accessed through two or more respective memory channels. Memory requests comprise a preference for energy savings or performance. The memory address map is associated with external memory devices and comprises an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively smaller power usage cases. The memory channel interleaver resides on the SoC and is configured to assign memory requests to the linear region or interleaved region according to the preference for power savings or performance. Brief Description of Drawings
    [0005] In the figures, similar numerical references refer to similar parts throughout the various views unless otherwise indicated. For numerical references with alphabetic character designations such as "102A" or "102B", the alphabetic character designations may differentiate two parts or similar elements present in the same figure. Alphabetic character designations for numerical references may be omitted when a reference number is intended to encompass all parts having the same numerical reference in all figures.
    [0006] Figure 1 is a block diagram of a system embodiment for providing energy selective memory channel interleaving or performance optimization;
    [0007] Fig. 2 is a flowchart illustrating one embodiment of a method implemented in the system of Fig. 1 for providing energy-selective memory channel interleaving or performance optimization.
    [0008] Fig. 3 is a data/flow chart illustrating the structure and operation of an illustrative memory address map in the system of Fig. 1;
    [0009] Fig. 4 is a block diagram/flow chart illustrating an embodiment of the memory channel interleaver of Fig. 1;
    [0010] Figure 5 is a flowchart illustrating an embodiment of a method of validating or eliminating high performance memory requests;
    [0011] Figure 6 illustrates another embodiment of a memory address map with a linear region and an interleaved region using four memory channels and two classifications;
    [0012] Figure 7 is a block diagram of an embodiment of a portable computer device comprising the system of Figure 1. Detailed Description
    [0013] The term "illustrative" is used here to mean "serving as an example, case or illustration". Any aspect described herein as "illustrative" is not necessarily to be regarded as preferred or advantageous over other aspects.
    [0014] In this description, the term "orders" may also include files having executable content, such as: object code, scripts, byte code, markup language files, and splices. Additionally, an "order" referred to herein may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
    [0015] The term "content" can also include files having executable content, such as: object code, scripts, byte code, markup language files, and splices. Additionally, "content" referred to herein may also include files that are not executable in nature, such as documents that need to be opened or other data files that need to be accessed.
    [0016] As used in this description, the terms "component", "database", "module", "system" and the like shall refer to a computer-related entity, be it hardware, firmware, a combination of hardware and software, software, or running software. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable element, an execution sequence, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components may reside within a process and/or sequence of execution, and a component may be located on one computer and/or distributed among two or more computers. Additionally, these components can be executed from various computer readable media having various data structures stored therein. Components may communicate through local and/or remote processes such as according to a signal having one or more packets of data (e.g. data from one component interacting with another component in a local system, distributed system, and/or or over a network such as the Internet with other signal systems).
    [0017] In this description, the terms "communication device", "wireless device", "cordless telephone", "wireless communication device" and "wireless device" are used interchangeably. With the advent of third-generation ("3G") and fourth-generation ("4G") wireless technology, greater availability of bandwidth has enabled more portable computing devices with a wider range of wireless capabilities. Therefore, a portable computing device may include a cell phone, a pager, a PDA, a smartphone, a navigation device, or a portable computer with a wireless connection or link.
    [0018] Fig. 1 illustrates a system 100 for providing performance-selective or power-optimized memory channel interleaving. System 100 may be implemented in any computing device, including a personal computer, a workstation, a server, a portable computing device (PCD) such as a cell phone, a portable digital assistant (PDA), a console game console, a palmtop computer, or a tablet computer.
    [0019] As illustrated in the embodiment of Figure 1, the system 100 comprises a System on Chip (SoC) 102 comprising various on-chip components and various external components connected to the SoC 102. The SoC 102 comprises one or more processing units, an interleaver channel memory 106, a storage controller 124, and embedded memory (e.g., a static random access memory (SRAM) 128, read-only memory (ROM) 130, etc.) interconnected by a SoC bus 107. storage controller 124 is electrically connected to and communicates with an external storage device 126. As is known in the art, memory channel interleaver 106 receives memory read/write requests associated with CPU 104 (or other memory clients). ) and distributes the memory data between two or more memory controllers, which are connected to the respective external memory devices via a dedicated memory channel. In the example of Figure 1, the system 100 comprises two memory devices 110 and 118. The memory device 110 is connected to the memory controller 108 and communicates through a first memory channel (CH0). Memory device 118 is connected to memory controller 116 and communicates through a second memory channel (CH1).
    [0020] It should be appreciated that any number of memory devices, memory controllers, and memory channels may be used in system 100 with any desired type, size, or configuration of memory (e.g., dual data rate memory ( DDR)). In the embodiment of Figure 1, the memory device 110 supported through the CH0 channel comprises two dynamic random access memory devices (DRAMs): a DRAM 112 and a DRAM 114. The memory device 118 supported through the CH1 channel also comprises two DRAM devices: one DRAM 120 and one DRAM 122.
    [0021] Memory channel interleaver 106 comprises a memory channel interleaver specially configured to selectively provide performance optimization and energy savings. Memory channel interleaver 106 is configured to selectively provide both high performance (interleaved) and low performance (linear) memory regions. Figure 3 illustrates an illustrative memory address map 300 controlled by memory channel interleaver 106. Memory address map 300 will be described to illustrate the general operation, architecture, and functionality of system 100 and memory channel interleaver. 106. Memory address map 300 corresponds to illustrative system 100 illustrated in Figure 1 with memory device 110 comprising DRAMs 112 and 114 (accessed via memory channel CH0) and memory device 118 comprising DRAMs 120 and 122 ( accessed through memory channel CH1).
    [0022] The memory address map 300 comprises a linear region 302 and an interleaved region 304. The linear region 302 can be used for relatively low power usage cases and/or tasks, and the interleaved region 304 can be used for use cases and/or relatively high energy tasks. Each region comprises a separately allocated memory address space with a corresponding address range divided between the two memory channels CH0 and CH1. The interleaved region 304 comprises an interleaved address space, and the linear region 302 comprises a linear address space.
    [0023] Referring to the example of figure 3, and with respect to the interleaved address space, a first address (address 0) can be assigned to a lower address associated with DRAM 114 and memory channel CH0. The next address in the interleaved address range (address 32) can be assigned to a lower address associated with DRAM 122 and the CH1 memory channel. In this way, a pattern of alternate addresses can be striped or interleaved through memory channels CH0 and CH1, ascending to the top or last address associated with DRAM 112 and DRAM 112, which defines a boundary between the interleaved region 304 and the linear region 302. In the interleaved region 304, the horizontal dashed arrows between CH0 and CH1 channels illustrate how the addresses performing "ping-pong" motion between memory channels. Clients requesting memory resources (e.g. CPU 104) for reading/writing data to memory devices can be served by both CH0 and CH1 memory channels as the data addresses can be considered random and therefore can be evenly distributed across both CH0 and CH1 channels.
    [0024] Linear region 302 comprises consecutive and separate memory address ranges within the same channel. As illustrated in the embodiment of Figure 3, a first range of consecutive memory addresses may be assigned to DRAM 112 in CH0, and a second range of consecutive addresses may be assigned to DRAM 120 in CH1. The next address in DRAM 112 above the interleaved/linear threshold can receive the first address (2N-3)*64) in the linear address space. Vertical arrows illustrate that consecutive addresses are assigned within CH0 until a last or higher address in DRAM 112 is reached (address (2N*64)). When the last available address in CH0 is reached, the next address in the linear address space can be assigned to the next available address in DRAM 120 above the interleaved/linear threshold (address (2N-2)*64+32). Then, the allocation scheme follows consecutive memory addresses in CH1 until a higher address is reached (address (2N-1)*64+32).
    [0025] Therefore, it should be appreciated that the low performance use case data can be contained completely in any CH0 channel or CH1 channel. In operation, only one of the CH0 and CH1 channels can be active while the other channel is placed in an idle or "auto-refresh" mode to conserve memory power. This can be extended to any number of N memory channels.
    [0026] Figure 2 illustrates a method 200 implemented by system 100 (Figure 1) for providing performance-selective or power-optimized memory channel interleaving. At block 202, a memory address map 300 is configured for available memory devices (e.g., DRAMs 112, 114, 120, and 122) accessed through two or more available channels (e.g., memory channels CH0 and CH1 ) with an interleaved region 304 and a linear region 302. The memory address map 300 can be configured based on high and low performance use cases, printing, or expected memory size. During initialization, based on the platform profile, memory channel interleaver 106 can provide a predetermined amount of interleaved and linear memory space. During runtime, an operating system may allocate interleaved region 304 for high performance client requests such as graphics processing unit (GPU), monitor, multimedia features, camera, etc. The operating system may allocate linear memory for client requests for relatively lower performance and/or for all other client requests. For example, linear region 302 can be allocated for operating system resources, general low performance applications, services, etc. It should be appreciated that memory may be dynamically allocated to the GPU for interleaved region 304. In other embodiments, referred to as static allocation, the GPU may utilize memory that has been predetermined, for example, during initialization to use interleaved region 304 in order to achieve high performance.
    [0027] In one embodiment, memory allocation for linear region 302 and interleaved region 304 can be configured based on desirable use cases. Memory allocation in different linear regions can be grouped based on use cases. For example, a first "energy-saving" use case might be allowed to access a first linear address space associated with CH0, and a second "energy-saving" use case might be allowed to access a second linear address space. linear address associated with CH1. In this way, memory power savings can be performed on the memory channel while the other is active.
    [0028]Referring again to Fig. 2, in block 204, memory channel interleaver 106 may receive memory requests from one or more clients (e.g. CPU 104) requesting memory resources. A memory request may include a "tip", parameters or other data indicating a preference for energy savings or performance. In one embodiment, the power/performance preference can be specified via a system call to an operating system. In that regard, system 100 may include an operating system (not illustrated) that provides memory allocation support. The operating system may have the ability to allocate memory from specific heaps as directed by a caller. Memory channel interleaver 106 and system 100 provide the ability to specify a type of memory (i.e. interleaved X linear) according to, for example, a degree of preference for energy savings X performance, and thus, achieve memory power savings and/or high bandwidth throughput.
    [0029] For example, non-uniform memory access (NUMA), which is used in multiprocessing, can perform memory allocation based on memory nodes relative to a processor (eg CPU 104). Under NUMA, a processor is aware of the difference in performance of different memory nodes, and may be able to intelligently allocate memory from preferred nodes. System 100 can implement this mechanism to allocate memory from a list of available nodes intelligently to allocate memory from the node that results in better performance or based on power consumption characteristics. Additionally, on some operating systems (e.g. Linux Android®), the memory allocator may have an input argument to indicate one or more memory stacks from which it is allocated, with the fallback ordered according to which memory stack. memory was the first to be added via calls during boot. Memory channel interleaver 106 can support such a mechanism to allocate memory from a specific stack type based on either performance or power consumption as requested by customers.
    [0030] In block 206, memory channel interleaver 106 assigns received memory requests to linear region 302 or interleaved region 304 according to the preference specified in the memory request (or otherwise) and the address map memory 300.
    [0031] As illustrated in method 500 of Fig. 5, memory channel interleaver 106 may also provide a mechanism for validating high-performance memory requests against a database comprising a bandwidth utilization history file. memory for specific types of tasks, processes, etc. At block 502, memory channel interleaver 106 may receive a high performance memory request associated with a new process. At block 504, the history file can be accessed to determine the memory bandwidth previously used by the process.
    [0032] In this way, memory requests can be allocated according to a historical trace of bandwidth demand for each task in progress. In one embodiment, transaction counters can be used to archive demand bandwidth for each of the tasks in progress on system 100 and accumulating a history for each process name, which can be stored on a file system or other memory. A memory manager can access the database when allocating memory to new tasks. As described above, the task can give a hint that it is high-performing or low-performing. The task can also specify whether the store is shareable. The memory manager can access the database to validate the request. If the high performance has not been empirically archived and justified, the memory allocator can negate the hint and allocate only low performance memory to save power. The memory allocator can also confirm that the store has been declared shareable and adhere to the original hint if it is shareable as a different task using the same shared store may require high bandwidth.
    [0033] Referring again to Fig. 5, in decision block 506, memory channel interleaver 106 determines whether the high performance memory request has been validated. If the previous bandwidth does not match a predetermined threshold for assignment to interleaved region 304, the memory request can be denied and instead assigned to linear region 302 (block 508). If the high-performance memory request is validated, however, the memory request can be assigned to the interleaved region (block 510).
    [0034] Figure 4 is a schematic diagram/flowchart illustrating the architecture, operation and/or functionality of an embodiment of memory channel interleaver 106. Memory channel interleaver 106 receives the record on the SoC bus 107 and provides outputs for memory controllers 108 and 116 (memory channels CH0 and CH1, respectively) via separate memory controller buses. The memory controller buses can run at half the rate of the SoC 107 bus with net data throughput being matched. Address mapping modules 450 can be programmed via the SoC bus 107. Address mapping modules 450 can configure and access address memory map 300 as described above, with linear region 302 and interleaved region 304. Data traffic entering the SoC bus 107 is routed to a data selector 470, which sends the data to memory controllers 108 and 116 via mixing components 472 and 474, respectively, based on a select signal 464 provided by the address mapping modules 450. For each traffic packet, a high address 456 enters the address mapping module 450. The address mapping modules 450 compare the high address 456 with the pre-interleaved and linear region addresses. programmed, performs address bit position reordering, and then sends it to a high address CH0 460 or high address CH1 462 based on interleaving parameters. Selection signal 464 specifies whether CH0 or CH1 has been selected. The hash components 472 and 474 may comprise a recombination of high addresses 460 and 462, low address 405, and CH0 data 466 and CH1 data 468.
    [0035] Fig. 6 illustrates another embodiment of a memory address map 600 adapted for four memory channels and using a plurality of classifications. Memory address map 600 adds two memory channels CH2 and CH3, compared to memory address map 300 (Figure 3) discussed above. Memory channel CH2 is associated with additional DRAMs 602 and 604. Memory channel CH3 is associated with additional DRAMs 606 and 608. As illustrated in Figure 6, memory address map 600 provides a classification scheme (classification 1 and rank 0), each with custom interleaving settings to provide a desired balance between performance and power consumption. Linear region 302 may be at rank 1 and utilize, for example, a Bank-Row-Column (BRC) DRAM interleaving mechanism to provide energy savings. A first part 610 of interleaved region 304 (which resides in DRAMs 112, 120, 602, and 606) may also be in rank 1 and utilize a Row-Bank-Column DRAM interleaving mechanism for performance. A second part 612 of interleaved region 304 (which encompasses all available memory in DRAMs 114, 122, 604, and 608) may be of a different rank (i.e., rank 0). DRAMs 114, 122, 604, and 608 can enter rank 0 using the DRAM BRC interleaving mechanism for performance.
    [0036] As mentioned above, System 100 can be embedded in any desirable operating system. Figure 7 illustrates system 100 incorporated into an illustrative portable computing device (PCD) 700. System 100 may be included in SoC 322, which may include a multi-core CPU 402A. The multi-core CPU 402A may include a zero core 410, a first core 412, and an N core 414. One of the cores may comprise, for example, a graphics processing unit (GPU) with one or more of the others comprising the CPU. 104 (figure 1). According to alternative illustrative embodiments, the CPU 402a may also comprise single core types rather than one having multiple cores, in which case the CPU 104 and GPU may be dedicated processors, as illustrated in system 100.
    [0037] A display controller 328 and a touch screen controller 330 can be coupled to the CPU 402a. In turn, touch screen monitor 108 external to system on chip 322 can be coupled to display controller 328 and touch screen controller 330.
    [0038] Figure 7 further illustrates that a 334 video encoder, e.g., a phase-shifting line (PAL) encoder, a sequential color a memoire (SECAM) encoder, or a national television systems committee encoder (NTSC), is coupled to the 402A multi-core CPU. Additionally, a video amplifier 336 is coupled to the video encoder 334 and the touch screen monitor 108. In addition, a video port 338 is coupled to the video amplifier 336. As illustrated in Figure 7, a serial bus controller universal (USB) 340 is coupled to the 402A multi-core CPU. In addition, a USB 342 port is coupled to the USB 340 controller. Memory 404A and a subscriber identity module (SIM) card 346 can also be coupled to the 402A multi-core CPU. Memory 404A may comprise memory devices 110 and 118 (Figure 1), as described above. System 100 (FIG. 1) can be coupled to CPU 402A.
    [0039] Additionally, as illustrated in Figure 7, a digital camera 348 can be coupled to the multi-core CPU 402A. In an illustrative aspect, the digital camera 348 is a charge coupled device (CCD) camera or a complementary metal oxide semiconductor (CMOS) camera.
    [0040] As further illustrated in Figure 7, a stereo audio encoder-decoder (CODEC) 350 can be coupled to the multi-core CPU 402A. In addition, an audio amplifier 352 may be coupled to the stereo audio CODEC 350. In an illustrative aspect, a first stereo speaker 354 and a second stereo speaker 356 are coupled to the audio amplifier 352. Figure 7 illustrates that an amplifier microphone 358 may also be coupled to stereo audio CODEC 350. Additionally, a microphone 360 may be coupled to microphone amplifier 358. In one particular aspect, a frequency modulation (FM) radio tuner 362 may be coupled to the microphone amplifier 358. 350 stereo audio CODEC. In addition, a 364 FM antenna is coupled to the 362 FM radio tuner. Additionally, 366 stereo headphones can be coupled to the 350 stereo audio CODEC.
    [0041] Figure 7 further illustrates that a radio frequency (RF) transceiver 368 can be coupled to the multi-core CPU 402A. An RF switch 370 can be coupled to the RF transceiver 368 and an RF antenna 372. As illustrated in Figure 7, a keyboard 204 can be coupled to the multi-core CPU 402A. In addition, a mono headset with a 376 microphone can be coupled to the 402A multi-core CPU. Additionally, a vibrator device 378 may be coupled to the multi-core CPU 402A.
    [0042] Figure 7 also illustrates that a power supply 380 can be coupled to system-on-chip 322. In one particular aspect, the power supply 380 is a direct current (DC) power supply that supplies power to various PCD 700 components that acquire power. Additionally, in one particular aspect, the power supply is a rechargeable DC battery or a DC power supply that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source.
    [0043] Figure 7 further indicates that PCD 700 may also include a network card 388 that may be used to access a data network, for example, a local area network, a personal area network, or any other network. The 388 network card can be a Bluetooth network card, a WiFi network card, a Personal Area Network (PAN) card, a Personal Area Network Ultra Low Energy Technology (PeANUT) network card, a television/cable/satellite tuner, or any other network card well known in the art. Additionally, network card 388 may be embedded in a chip, that is, network card 388 may be a complete one-chip solution, and may not be a separate network card 388.
    [0044] As shown in figure 7, touch screen monitor 108, video port 338, USB port 342, camera 348, first stereo speaker 354, second stereo speaker 356, microphone 360, FM antenna 364, stereo headphones 366, RF switch 370, RF antenna 372, keyboard 374, mono headset 376, vibrator 378, power supply 380 can be external to system-on-chip 322.
    [0045] It should be appreciated that one or more of the method steps described here may be stored in memory as computer program instructions, such as modules described above. These instructions can be executed by any suitable processor in combination with the corresponding module to carry out the methods described here.
    [0046] Certain steps in the processes or process flows in this specification naturally precede others for the invention to function as described. However, the invention is not limited to the order of the steps described if such order or sequence does not alter the functionality of the invention. That is, it is recognized that some steps may be performed before, after or in parallel (substantially simultaneously) with other steps without departing from the scope and spirit of the invention. In some cases, certain steps may be omitted or not performed without departing from the invention. Additionally, words like "henceforth", "then", "hereafter", etc. should not limit the order of steps. These words are simply used to guide the reader through the description of the illustrative method.
    [0047] Additionally, one skilled in the programming art can write computer code or identify suitable hardware and/or circuits for implementing the described invention without difficulty based on the flowcharts and associated description in that specification, for example.
    [0048] Therefore, the description of a particular set of program code instructions or detailed hardware devices is not considered necessary for a proper understanding of how to create and make use of the invention. The inventive functionality of the claimed computer-implemented processes is explained in greater detail in the above description and in conjunction with figures which may illustrate various process flows.
    [0049] In one or more illustrative aspects, the functions described may be implemented in hardware, software, firmware or any combination thereof. If implemented in software, functions can be stored in or transmitted as one or more instructions or code on a computer-readable medium. Computer readable medium includes both computer storage medium and communication medium including any medium that facilitates the transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer readable medium may comprise RAM, ROM, EEPROM, NAND flash, NOR flash, M-RAM, P-RAM, R-RAM, CD-ROM or other optical disk storage. , magnetic disk storage or other magnetic storage devices, or any other medium that can be used to port or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
    [0050] Also, any connection is properly called a computer-readable medium. For example, if the software is transmitted from a network site, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line ("DSL"), or wireless technologies wire such as infrared, radio and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwave are included in the definition of medium.
    [0051] Floppy disk and disk, as used herein, include compact disk ("CD"), laser disk, optical disk, digital versatile disk ("DVD"), floppy disk and blu-ray disk where floppy disks normally reproduce the data magnetically, while discs reproduce data optically with lasers. Combinations of the above must also be included within the scope of the computer readable medium.
    [0052] Alternative modalities will become apparent to those versed in the technique to which the invention belongs without departing from its spirit and scope. Therefore, while selected aspects have been illustrated and described in detail, it will be understood that various substitutions and changes may be made herein without departing from the spirit and scope of the present invention, as defined by the following claims.
    权利要求:
    Claims (13)
    [0001]
    1. Memory channel interleaving (200) method with selective energy or performance optimization, the method characterized in that it comprises: setting (202) a memory address map (300) for at least a first device memory device (110) and a second memory device (118), wherein the first memory device (110) is connected to a first memory controller (108) and communicates through a first memory channel (CH0) and wherein the second memory device (118) is connected to a second memory controller (116) and communicates over a second memory channel (CH1), wherein the memory address map (300) comprises a linear region (302) and an interleaved region (304), each region (302, 304) comprising separate allocated memory address space with a corresponding address range divided between the two memory channels (CH0, CH1), the interleaved region (304) ) comprising an inter-address space draught for relatively higher performance use cases and the linear region (302) comprising a linear address space for relatively lower power use cases; the receive (204), in a memory channel interleaver (106), of memory requests from one or more clients (104), the memory requests comprising a preference for energy savings or performance; the assignment (206) by the memory channel interleaver (106) of memory requests to the region linear (302) or interleaved region (304) according to preference for energy savings or performance, wherein linear address comprises a first address range associated with the first memory device (110) and accessed through the first memory channel (CH0) and a second address range associated with the second memory device (118) and accessed through the second memory channel (CH1), wherein the assignment of memory requests to the linear region (302) comprises using the first address range associated with the first memory device (110) while the second memory device (118) is placed in a power saving mode, wherein the method further comprises:a validating memory requests having the performance preference with a database comprising a memory bandwidth history file; and if not validated, eliminating the performance preference and assigning the non-validated memory request to the linear region (302).
    [0002]
    2. Method according to claim 1, characterized in that it additionally comprises when a last memory address in the first address range of the linear region (302) is reached: placing the first memory device (110) in mode power saving; activating the second memory device (118); and assigning a next received memory request comprising the power saving preference to a first memory address corresponding to the second address range associated with the second memory device (118).
    [0003]
    3. Method according to claim 1, characterized in that the preference for energy savings or performance is specified through a system call to an operating system.
    [0004]
    4. Method according to claim 1, characterized in that the preference for energy savings or performance comprises a parameter specifying a type of memory stack.
    [0005]
    5. Method according to claim 1, characterized in that the memory devices (110, 118) comprise dynamic random access memory devices, DRAM (112, 114, 120, 122).
    [0006]
    6. Method according to claim 1, characterized in that the channel interleaver (106) receives memory requests through a System-on-Chip, SOC (107) bus.
    [0007]
    7. Method according to claim 1, characterized in that the assignment of memory requests to the linear region (302) or interleaved region (304) comprises dynamic memory allocation or predetermined static memory allocation.
    [0008]
    8. System for providing energy selective memory channel interleaving or performance optimization, the system characterized in that it comprises: means for configuring (202) a memory address map (300) for at least a first storage device; memory (110) and a second memory device (118), wherein the first memory device (110) is connected to a first memory controller (108) and is configured to communicate over a first memory channel (CH0) ) and wherein the second memory device (118) is connected to a second memory controller (116) and communicates over a second memory channel (CH1), wherein the memory address map (300) comprises a linear region (302) and an interleaved region (304), each region (302, 304) comprising separate allocated memory address space with a corresponding address range divided between the two memory channels (CH0, CH1), the interleaved region (304) buy comprising an interleaved address space for relatively higher performance use cases and the linear region (302) comprising a linear address space for relatively lower power use cases; means for receiving (204) memory requests from one or more clients (104), the memory requests comprising a preference for energy savings or performance; the assignment (206) of the memory requests to the linear region (302) or interleaved region (304) according to the preference for energy savings or performance, wherein linear address comprises a first address range associated with the first memory device (110) and accessed through the first memory channel (CH0) and a second address range associated with the second memory device (118) and accessed through the second memory channel (CH1), wherein the assignment of memory requests to the linear region (302) comprises using the first address range associated with the first memory device (110) while the second memory device (118) is placed in a power saving mode, wherein the system further comprises: means for validating memory requests having the preference by performance with a database comprising a memory bandwidth history file; and means for eliminating the performance preference for non-validated memory requests and assigning the non-validated memory request to the linear region (302).
    [0009]
    9. System according to claim 8, characterized in that it additionally comprises when a last memory address in the first address range of the linear region (302) is reached: means for placing the first memory device (110) in the power saving mode; means for activating the second memory device (118); and means for designating a next received memory request comprising the power saving preference for a first memory address corresponding to the second address range associated with the second memory device (118).
    [0010]
    10. System according to claim 8, characterized in that the preference for energy savings or performance is specified through a system call to an operating system.
    [0011]
    11. System according to claim 8, characterized in that the preference for energy savings or performance comprises a parameter specifying a type of memory stack.
    [0012]
    12. System according to claim 8, characterized in that the memory devices (110, 118) comprise dynamic random access memory devices, DRAM (112, 114, 120, 122).
    [0013]
    13. Memory, characterized in that it comprises instructions that, when executed, cause a computer to perform a method as defined in any one of claims 1 to 7.
    类似技术:
    公开号 | 公开日 | 专利标题
    BR112016002454B1|2022-01-04|SYSTEM AND METHOD FOR MEMORY CHANNEL INTERCALING WITH SELECTIVE ENERGY OR PERFORMANCE OPTIMIZATION
    US10067865B2|2018-09-04|System and method for allocating memory to dissimilar memory devices using quality of service
    JP6378325B2|2018-08-22|System and method for uniformly interleaving data across a multiple channel memory architecture with asymmetric storage capacity
    TWI525435B|2016-03-11|System, method and computer program product for dynamically allocating memory in a memory subsystem having asymmetric memory components
    JP2018518739A|2018-07-12|System and method for optimizing memory power consumption in heterogeneous system memory
    JP2019523945A|2019-08-29|System and method for odd modulus memory channel interleaving
    TW201717026A|2017-05-16|System and method for page-by-page memory channel interleaving
    TW201729113A|2017-08-16|System and method for memory channel interleaving using a sliding threshold address
    US9575881B2|2017-02-21|Systems and methods for providing improved latency in a non-uniform memory architecture
    US20170212581A1|2017-07-27|Systems and methods for providing power efficiency via memory latency control
    US20180365425A1|2018-12-20|Systems and methods for securely booting a system on chip via a virtual collated internal memory pool
    US20170108911A1|2017-04-20|System and method for page-by-page memory channel interleaving
    EP3427153B1|2020-05-27|Multi-rank collision reduction in a hybrid parallel-serial memory system
    US9542333B2|2017-01-10|Systems and methods for providing improved latency in a non-uniform memory architecture
    CN111104219A|2020-05-05|Binding method, device, equipment and storage medium of virtual core and physical core
    同族专利:
    公开号 | 公开日
    CN105452986B|2018-06-12|
    EP3030949A1|2016-06-15|
    JP2016529618A|2016-09-23|
    KR20160040289A|2016-04-12|
    US20150046732A1|2015-02-12|
    CA2918091A1|2015-02-12|
    KR101753020B1|2017-07-03|
    CN105452986A|2016-03-30|
    US9612648B2|2017-04-04|
    CA2918091C|2021-03-02|
    WO2015021316A1|2015-02-12|
    EP3030949B1|2019-05-22|
    BR112016002454A2|2017-08-01|
    JP6178512B2|2017-08-09|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    EP1050819A1|1999-05-03|2000-11-08|Sgs Thomson Microelectronics Sa|Computer memory access|
    US7081897B2|2003-12-24|2006-07-25|Intel Corporation|Unified memory organization for power savings|
    JP4569921B2|2004-08-04|2010-10-27|パナソニック株式会社|Power-saving memory access control device|
    US8010764B2|2005-07-07|2011-08-30|International Business Machines Corporation|Method and system for decreasing power consumption in memory arrays having usage-driven power management|
    US7793059B2|2006-01-18|2010-09-07|Apple Inc.|Interleaving policies for flash memory|
    US20070180203A1|2006-02-01|2007-08-02|Madhusudhan Ramgarajan|Optimizing system performance in flexible interleaving memory mode|
    JP2008152687A|2006-12-20|2008-07-03|Matsushita Electric Ind Co Ltd|Memory controller|
    US7739461B2|2007-07-10|2010-06-15|International Business Machines Corporation|DRAM power management in a memory controller|
    US7882319B2|2007-09-27|2011-02-01|Oracle America Inc.|Method and system for memory management|
    KR20100100395A|2009-03-06|2010-09-15|삼성전자주식회사|Memory system having multiple processors|
    US8245060B2|2009-10-15|2012-08-14|Microsoft Corporation|Memory object relocation for power savings|
    US8321703B2|2009-12-12|2012-11-27|Microsoft Corporation|Power aware memory allocation|
    US9043548B2|2010-01-28|2015-05-26|Cleversafe, Inc.|Streaming content storage|
    JP5678273B2|2010-03-01|2015-02-25|パナソニックＩｐマネジメント株式会社|Memory controller|
    JP2011227664A|2010-04-19|2011-11-10|Toshiba Corp|Memory system|
    US20110320751A1|2010-06-25|2011-12-29|Qualcomm Incorporated|Dynamic Interleaving Of Multi-Channel Memory|
    US8422315B2|2010-07-06|2013-04-16|Winbond Electronics Corp.|Memory chips and memory devices using the same|
    US9235500B2|2010-12-07|2016-01-12|Microsoft Technology Licensing, Llc|Dynamic memory allocation and relocation to create low power regions|
    US20120179883A1|2011-01-12|2012-07-12|Broadcom Corpotation|System and method for dynamically adjusting memory performance|
    US8819379B2|2011-11-15|2014-08-26|Memory Technologies Llc|Allocating memory based on performance ranking|
    US20130268984A1|2012-04-10|2013-10-10|Comcast Cable Communications, Llc|Data network traffic management|
    US9256531B2|2012-06-19|2016-02-09|Samsung Electronics Co., Ltd.|Memory system and SoC including linear addresss remapping logic|
    JP6000708B2|2012-07-20|2016-10-05|キヤノン株式会社|Memory control apparatus and method|
    US9086957B2|2012-08-02|2015-07-21|International Business Machines Corporation|Requesting a memory space by a memory controller|
    US9110795B2|2012-12-10|2015-08-18|Qualcomm Incorporated|System and method for dynamically allocating memory in a memory subsystem having asymmetric memory components|
    JP5885651B2|2012-12-27|2016-03-15|株式会社東芝|Address generation circuit|
    US20140310503A1|2013-04-12|2014-10-16|Texas Instruments Incorporated|Memory interleaving on memory channels|US9256531B2|2012-06-19|2016-02-09|Samsung Electronics Co., Ltd.|Memory system and SoC including linear addresss remapping logic|
    KR102355573B1|2014-10-29|2022-01-27|삼성전자주식회사|MEMORY SYSTEM AND SoC INCLUDING LINEAR REMAPPER AND ACCESS WINDOW|
    US20170108911A1|2015-10-16|2017-04-20|Qualcomm Incorporated|System and method for page-by-page memory channel interleaving|
    US20170108914A1|2015-10-16|2017-04-20|Qualcomm Incorporated|System and method for memory channel interleaving using a sliding threshold address|
    US20170109090A1|2015-10-16|2017-04-20|Qualcomm Incorporated|System and method for page-by-page memory channel interleaving|
    US20170162235A1|2015-12-02|2017-06-08|Qualcomm Incorporated|System and method for memory management using dynamic partial channel interleaving|
    US20170262367A1|2016-03-11|2017-09-14|Qualcomm Incorporated|Multi-rank collision reduction in a hybrid parallel-serial memory system|
    US10140223B2|2016-06-27|2018-11-27|Qualcomm Incorporated|System and method for odd modulus memory channel interleaving|
    CN106201905B|2016-07-11|2019-09-24|浪潮电子信息产业有限公司|A kind of memory addressing method|
    KR20180007374A|2016-07-12|2018-01-23|삼성전자주식회사|Electronic device performing software training on memory channel and memory channel training method thereof|
    CN106991007B|2017-03-31|2019-09-03|青岛大学|A kind of data processing method and equipment based on GPU on piece|
    CN107291537A|2017-06-07|2017-10-24|江苏海平面数据科技有限公司|The optimization method that memory space is used on a kind of GPU pieces|
    KR102178931B1|2018-02-21|2020-11-13|서강대학교 산학협력단|Method for predicting energy consumption of heap memory object and memory system implementing the same|
    US10628308B2|2018-05-24|2020-04-21|Qualcomm Incorporated|Dynamic adjustment of memory channel interleave granularity|
    WO2019237261A1|2018-06-12|2019-12-19|华为技术有限公司|Memory management method, device and system|
    CN108845958A|2018-06-19|2018-11-20|中国科学院软件研究所|A kind of mapping of interleaver and dynamic EMS memory management system and method|
    EP3822796A4|2018-07-31|2021-07-21|Huawei Technologies Co., Ltd.|Memory interleaving method and device|
    KR102187213B1|2019-01-24|2020-12-04|서강대학교 산학협력단|Method for allocating heap memory objects and hybrid memory system implementing the same|
    US11256318B2|2019-08-09|2022-02-22|Intel Corporation|Techniques for memory access in a reduced power state|
    CN113157602A|2020-01-07|2021-07-23|中科寒武纪科技股份有限公司|Method and device for distributing memory and computer readable storage medium|
    法律状态:
    2020-03-10| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2021-11-03| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2022-01-04| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 07/08/2014, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US13/962,746|2013-08-08|
    US13/962,746|US9612648B2|2013-08-08|2013-08-08|System and method for memory channel interleaving with selective power or performance optimization|
    PCT/US2014/050208|WO2015021316A1|2013-08-08|2014-08-07|System and method for memory channel interleaving with selective power or performance optimization|
    [返回顶部]